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| DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear September 1986 Revised February 2000 DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description The DM74ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. Features s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with Schottky and LS TTL counterpart s Improved AC performance over LS74 at approximately half the power Ordering Code: Order Number DM74ALS74AM DM74ALS74ASJ DM74ALS74AN Package Number Package Description M14A M14D N14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Function Table Inputs PR L H L H H H CLR H L L H H H CLK X X X L D X X X H L X Q H L H (Note 1) H L Q0 Outputs Q L H H (Note 1) L H Q0 L = LOW State H = HIGH State X = Don't Care = Positive Edge Transition Q0 = Previous Condition of Q Note 1: This condition is nonstable; it will not persist when preset and clear inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the VOH specification. (c) 2000 Fairchild Semiconductor Corporation DS006109 www.fairchildsemi.com DM74ALS74A Logic Diagram www.fairchildsemi.com 2 DM74ALS74A Absolute Maximum Ratings(Note 2) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 87.0C/W 117.0C/W 7V 7V 0C to +70C -65C to +150C Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tW(CLK) tW tSU Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Width of Clock Pulse Pulse Width Preset & Clear Data Setup Time HIGH LOW LOW Data PRE or CLR Inactive tH TA Data Hold Time Free Air Operating Temperature 0 14.5 14.5 14.5 15 (Note 3) 10 (Note 3) 0 (Note 3) 0 70 ns ns C Parameter Min 4.5 2 0.8 -0.4 8 34 Nom 5 Max 5.5 Units V V V mA mA MHz ns ns ns Note 3: The () arrow indicates the positive edge of the Clock is used for reference. 3 www.fairchildsemi.com DM74ALS74A Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25C. Symbol VIK VOH VOL II IIH IIL IO ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current Conditions VCC = 4.5V, II = -18 mA IOH = -0.4 mA VCC = 4.5V to 5.5V VCC = 4.5V VIH = 2V VCC = 5.5V, VIH = 7V VCC = 5.5V, VIH = 2.7V VCC = 5.5V, VIL = 0.4V VCC = 5.5V, VO = 2.25V VCC = 5.5V (Note 4) IOL = 8 mA Clock, D Preset, Clear Clock, D Preset, Clear Clock, D Preset, Clear (Note 5) -30 2.4 VCC - 2 0.35 0.5 0.1 0.2 20 40 -0.2 -0.4 -112 4 Min Typ Max -1.5 Units V V V mA A mA mA mA Note 4: ICC is measured with D, CLK and PRESET grounded, then with D, CLK and CLEAR grounded. Note 5: IIL PRE and CLR pins not guaranteed to meet specifications with both PRE and CLK LOW. Switching Characteristics over recommended operating free air temperature range. Parameter fMAX tPLH tPHL tPLH tPHL Conditions VCC = 4.5V to 5.5V RL = 500 CL = 50 pF Preset or Clear Q or Q From To Min 34 3 5 5 5 13 15 16 18 Max Units MHz ns ns ns ns Clock Q or Q www.fairchildsemi.com 4 DM74ALS74A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com DM74ALS74A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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